“Reduced-Pin-Count BOST for Test-Cost Reduction” Youngkwang Lee, Young-woo Lee, Sungyoul Seo, Sungho Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) Accepted, 2021 “Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks” Young-woo Lee, Hyeonchan Lim, Youngkwang Lee, Sungho Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) vol.39, no.10, pp.3023-3034, October 2020 “Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing” Sungyoul Seo, Young-woo Lee, Hyeonchan Lim, Sungho Kang IEEE Transactions on Semiconductor Manufacturing (IEEE TSM) vol.33, no.3, pp.391-403, August 2020 “A Low-cost Concurrent TSV Test Architecture with Lossless Test Output Compression Scheme” Young-woo Lee, Hyeonchan Lim, Sungyoul Seo, Keewon Cho, Sungho Kang Public Library of Science One (PLOS ONE) vol.14, no.8, pp e0221043, August 2019 “An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults” Keewon Cho, Young-woo Lee, Sungyoul Seo, Sungho Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) vol.38, no.3, pp.551-561 , March 2019 “Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost” Inhyuk Choi, Hyunggoy Oh, Young-woo Lee, Sungho Kang IEEE Transactions on Computers (IEEE TCOM) vol.67, no.12, pp1835-1839, December 2018 “A Statistic-based Scan Chain Reordering for Energy-Quality Scalable Scan Test “ Sungyoul Seo, Keewon Cho, Young-woo Lee, Sungho Kang IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE JETCAS) vol.8, no.3, pp 391-403, September 2018 “Grouping-based TSV Test Architecture for Resistive Open and Bridge Defects in 3D-ICs” Young-woo Lee, Hyeonchan Lim, and Sungho Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) vol.36, no.10, pp.1759-1763, October 2017