Research Area

We focus on the research about the VLSI / SoC design issues and architecture challenges for intelligent, biomedical, automotive and mobile systems. Our research interests lie primarily in the area of VLSI / SoC / 3D IC design, test methodology, IC reliability and hardware security. For more details on our research, please refer to the following information and our publications.

■ VLSI/SoC/3D IC Design Technology
– Parallel Processing: biomedical processor, high-performance computing (HPC)
– Artificial Intelligence (AI): AI accelerator, deep neural network
– Reliability: automotive IC, high-bandwidth memory (HBM)

■ VLSI/SoC/3D IC Testing Technology
– Test Methodology: reduced pin count test (RPCT), massive parallel test (MPT)
– Scan Test: compression, low power test, diagnosis, test access mechanism
– Through Silicon Via (TSV): test structure, test optimization, TSV repair

■ Hardware Security and Robust Design Methodology
– Security and Trust: detection/protection circuits against physical attacks
– Design Methodology: design-for-testability, design-for-security, design-for-reliability

■ Memory Test and Repair Methodology
– Memory Test: built-in self test (BIST), 3D-DRAM control, built-off self test (BOST)
– Memory Repair: redundancy analysis (RA), built-in RA (BIRA), built-in self-repair (BISR)